1. Field of the Invention
The present invention relates to a memory device, and more particularly to a memory device, which combines a self-refresh enable signal and a power mode decision signal, thereby preventing an internal voltage Vcore from being dropped down without the increase of IDD3P current when the memory device performs a self-refresh operation.
2. Description of the Prior Art
Generally, a memory device includes an operation state and a stand-by state. In a stand-by state, a memory device performs a self-refresh operation for preservation of storage data. In a self-refresh operation, a memory device changes into a low power operation mode, thereby minimizing the power consumption, in contrast with an auto-refresh operation performed when the memory device is in an operation state. For this, the memory device uses only a stand-by mode internal voltage generator used in only a stand-by state instead of an operation mode internal voltage generator used in an operation state, thereby minimizing power consumption.
However, in the stand-by state of the memory device, operation characteristics of the stand-by mode internal voltage generator may change according to the change of pressure, volume and temperature. This change in the operation characteristics of the stand-by mode internal voltage generator may cause the increase of power consumption and become a factor of dropping down the voltage level of an internal voltage Vcore which is an output voltage.
The drop of the voltage level of the internal voltage has influence on an operation of a sense amplifier. Specifically, in a state in which the voltage level of the internal voltage is abnormally dropped down, the threshold voltage Vt of an NMOS transistor included in the sense amplifier may increase according to the change of a process, a voltage and temperature. Herein, the internal voltage having the dropped voltage level causes the voltage level of a bit line precharge voltage (Vblp=1/2Vcore) detected by the sense amplifier to be dropped down. Accordingly, the bit line precharge voltage Vblp having the dropped voltage level does not turn on an NMOS transistor for detecting data ‘0’ (i.e., ‘logic low’) stored in a memory cell, so that the sense amplifier does not normally operate.
As a result, in the stand-by state of the memory device, the voltage level of the internal voltage is dropped down, so that the sense amplifier may abnormally operate. The abnormal operation of the sense amplifier disturbs a normal self-refresh operation of the memory device.
In the prior art, in order to prevent the drop of the voltage level of the internal voltage when the memory device performs the self-refresh operation as described above, the operation mode internal voltage generator is used together with the stand-by mode internal voltage generator, so that the voltage level of the internal voltage can be constantly maintained. However, the conventional method may also increase IDD3P current used when the memory device is in a low power operation mode. Herein, the IDD3P current represents electric current used when the memory device is in the low power operation mode, that is, electric current consumed when only one bank of multiple banks included in the memory device is used.
FIG. 1 is a circuit diagram showing an operation mode entrance circuit of a memory device according to the prior art.
The conventional operation mode entrance circuit includes an input means 100 for receiving a clock enable signal CKE and a word line active command signal ACT, and a decoding means 110 for combining the clock enable signal CKE and the word line active command signal ACT, which are transferred through the input means 100, and outputting the combined signal.
In the conventional operation mode entrance circuit including the construction as described above, when the word line active command signal ACT is enabled to be in a ‘logic high’ state, whether an operation mode internal voltage generator operates or not is determined according to the state of the clock enable signal CKE. In other words, in a state where the word line active command signal ACT is enabled to be in the ‘logic high’ state, when the clock enable signal CKE is inputted in a ‘logic low’ state, the operation mode internal voltage generator does not operate. In contrast, when the clock enable signal CKE is inputted in a ‘logic high’ state, the operation mode internal voltage generator operates. That is, the clock enable signal CKE in the ‘logic high’ state represents an operation state of the memory device. In contrast, the clock enable signal CKE in the ‘logic low’ state represents a low power operation mode which is a stand-by state of the memory device.
Herein, a self-refresh operation of the memory device is performed in the stand-by state of the memory device, that is, the low power operation mode. Accordingly, in order to prevent the voltage level of an internal voltage from being dropped down in the self-refresh operation, when the operation mode internal voltage generator operates according to the conventional method, IDD3P current, which is electric current in the low power operation mode, may also increase. Therefore, it is difficult to operate the memory device with low power.